The present invention relates to initialization of non-volatile programmable latches.
Non-volatile programmable latches enable one to modify an integrated circuit without changing the fabrication masks. FIG. 1 illustrates one such latch 110 used to modify an integrated memory by replacing defective memory cells with spare memory cells. In latch 110, laser-programmable fuse F1 has one terminal connected to the drain of NMOS transistor 114 whose source is connected to ground. The other terminal of fuse F1 is connected to terminal 120 also connected to the drain of PMOS transistor 130. The source of transistor 130 is connected to power supply voltage VCC. The gates of transistors 130 and 114 are connected to the latch initialization input SET.
Terminal 120 is connected to the input of CMOS inverter 140 whose output OUT is connected to the gate of PMOS transistor 150. The source of transistor 150 is connected to power supply voltage VCC, and the drain to terminal 120.
The output OUT of inverter 140 is connected to memory decoders (not shown) that control selection of regular and spare memory cells.
The latch is initialized by a positive edge of signal SET. The input SET is initially kept at ground when the power is turned on. Consequently, transistor 130 pre-charges the terminal 120 to VCC. Then the input SET is driven high, turning off transistor 130 and turning on transistor 114. If the fuse F1 is intact, transistor 114 overpowers transistor 150 and drives the terminal 120 to ground. Inverter 140 shuts off transistor 150, latching the output OUT in the high voltage state.
If the fuse F1 has been blown, the terminal 120 remains high when SET becomes high. The output OUT remains low. Transistor 150 remains on, maintaining the high voltage on terminal 120.
The signal SET is generated by power up circuit 204 illustrated in FIG. 2. The input SET is connected to the output PU of the power up circuit. PMOS transistor 210 of the power up circuit is connected between power supply VCC and a terminal 220. The gate of transistor 210 is grounded. Four inverters 224, 230, 234, 240 are connected in series between the terminal 220 and the output terminal PU to provide a delay on output PU at power up. Additional delay is provided by capacitor 250 connected between terminal 220 and ground.
Initially when the power is turned on, signal PU remains low for a while due to the delay provided by the inverters and the capacitor. During the delay the voltage VCC develops and allows transistor 130 (FIG. 1) to charge the terminal 120 to a high voltage. Also during this delay, transistor 150 turns on.
When the delay ends, the input SET is driven high by inverter 240, allowing the output OUT to assume a voltage indicating the state of fuse F1.
Disadvantageously, the latch may operate improperly if VCC rises slowly during power up. Indeed, if VCC rises slowly, the output PU will almost track VCC. Therefore, transistor 130 may never turn on, or at least it may never turn on sufficiently strongly or for a sufficient period of time to charge the terminal 120 to a high voltage. Consequently, if the fuse F1 is blown, the terminal 120 can get stuck at some intermediate voltage between VCC and ground, and so can the output OUT.
It is desirable to provide more reliable latch initialization.